Invention Grant
- Patent Title: 3D-interconnect
-
Application No.: US17340469Application Date: 2021-06-07
-
Publication No.: US11929337B2Publication Date: 2024-03-12
- Inventor: Chok J. Chia , Qwai H. Low , Patrick Variot
- Applicant: Invensas LLC
- Applicant Address: US CA San Jose
- Assignee: Invensas LLC
- Current Assignee: Invensas LLC
- Current Assignee Address: US CA San Jose
- Agency: HALEY GUILIANO LLP
- The original application number of the division: US15493917 2017.04.21
- Main IPC: H01L21/52
- IPC: H01L21/52 ; H01L21/56 ; H01L23/00 ; H01L23/538 ; H01L25/065 ; H01L23/31 ; H01L23/498 ; H01L25/10

Abstract:
A microelectronic assembly comprises a microelectronic element, a redistribution structure, a plurality of backside conductive components and an encapsulant. The redistribution structure may be configured to conductively connect bond pads of the microelectronic element with terminals of the microelectronic assembly. The plurality of back side conductive components may be etched monolithic structures and further comprise a back side routing layer and an interconnection element integrally formed with the back side routing layer and extending in a direction away from the back side routing layer. The back side routing layer of at least one of the plurality of back side conductive components overlies the rear surface of the microelectronic element. An encapsulant may be disposed between each interconnection element. The back side routing layer of the at least one of the plurality of back side conductive components extends along one of the opposed interconnection surfaces.
Public/Granted literature
- US20210366857A1 3d-Interconnect Public/Granted day:2021-11-25
Information query
IPC分类: