Invention Grant
- Patent Title: Electronic memory devices
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Application No.: US17614813Application Date: 2020-05-28
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Publication No.: US11929120B2Publication Date: 2024-03-12
- Inventor: Manus Hayne , Dominic Lane
- Applicant: University of Lancaster
- Applicant Address: GB Lancaster
- Assignee: University of Lancaster
- Current Assignee: University of Lancaster
- Current Assignee Address: GB Lancaster
- Agency: Young Basile Hanlon & MacFarlane, P.C.
- Priority: GB 07540 2019.05.29
- International Application: PCT/GB2020/051292 2020.05.28
- International Announcement: WO2020/240186A 2020.12.03
- Date entered country: 2021-11-29
- Main IPC: G11C16/10
- IPC: G11C16/10 ; G11C16/04 ; H01L29/788 ; H10B43/35

Abstract:
A memory cell comprises a floating gate being disposed between a control gate and a channel, the floating gate being electrically isolated from the control gate and the channel by charge barriers and being configured to enable the selective passage of charge carriers into and out of the floating gate to provide occupancy states of the floating gate. The channel is arranged to provide a minimum threshold voltage to be applied between a control gate and the substrate for introducing charge carriers into the channel from the substrate to make the channel conductive, the minimum threshold voltage being dependent on the occupancy state of the floating gate, such that a read voltage may be applied between the control gate and the substrate that will provide a conductive channel for a first occupancy state of the floating gate and a non-conductive channel for a second occupancy state of the floating gate.
Public/Granted literature
- US20220230686A1 Improvements Relating to Electronic Memory Devices Public/Granted day:2022-07-21
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