Invention Grant
- Patent Title: Method for manufacturing a semiconductor device with reduced variation of the impurity concentration near the surface of the semiconductor film
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Application No.: US17476558Application Date: 2021-09-16
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Publication No.: US11894447B2Publication Date: 2024-02-06
- Inventor: Tetsuya Yamamoto
- Applicant: LAPIS SEMICONDUCTOR CO., LTD.
- Applicant Address: JP Yokohama
- Assignee: Lapis Semiconductor Co., Ltd.
- Current Assignee: Lapis Semiconductor Co., Ltd.
- Current Assignee Address: JP Yokohama
- Agency: Volentine, Whitt & Francos, PLLC
- Priority: JP 20163679 2020.09.29
- Main IPC: H01L21/66
- IPC: H01L21/66 ; H01L21/3213 ; H01L29/66 ; H01L29/423 ; H01L29/788 ; H01L21/266

Abstract:
A method for manufacturing a semiconductor device includes: implanting a P-type impurity from a region where the first conductor film is formed toward an inside of the semiconductor substrate with a first acceleration energy; forming a nitride film provided with a first opening on the first conductor film; forming an insulating film with a second opening from which the first conductor film is exposed; forming a second conductor film to fill the second opening of the insulating film; removing the nitride film and a portion of the first conductor film positioned below the nitride film to expose the oxide film in a peripheral area of a formation region of the insulating film; and implanting the P-type impurity from a region from which the oxide film is exposed toward an inside of the semiconductor substrate with a second acceleration energy smaller than the first acceleration energy.
Public/Granted literature
- US20220102536A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE Public/Granted day:2022-03-31
Information query
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