Invention Grant
- Patent Title: Power management circuit in low-power double data rate memory and management method thereof
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Application No.: US17704152Application Date: 2022-03-25
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Publication No.: US11894043B2Publication Date: 2024-02-06
- Inventor: Shuenrun Seara Jian
- Applicant: Integrated Silicon Solution Inc.
- Applicant Address: US CA Milpitas
- Assignee: INTEGRATED SILICON SOLUTION INC.
- Current Assignee: INTEGRATED SILICON SOLUTION INC.
- Current Assignee Address: US CA Milpitas
- Agency: McClure, Qualey & Rodack, LLP
- Priority: TW 0141428 2021.11.05
- Main IPC: G11C5/14
- IPC: G11C5/14 ; G11C11/4074 ; G05F1/56 ; G11C5/02

Abstract:
A power management circuit in a low-power double data rate memory is configured to manage a plurality of power supplies memory according to a reference voltage. A low dropout regulator has a first transmitting terminal and a second transmitting terminal. The low dropout regulator adjusts a voltage difference between a first voltage and a second voltage according to the reference voltage. A power network structure is electrically connected to the low dropout regulator. A first power network circuit has a first connecting point, a grid shape and a first unit network space. A second power network circuit has a second connecting point, another grid shape and a second unit network space. The second connecting point is separated from the first connecting point by a distance. The distance is smaller than or equal to one of the first unit network space and the second unit network space.
Public/Granted literature
- US20230140988A1 POWER MANAGEMENT CIRCUIT IN LOW-POWER DOUBLE DATA RATE MEMORY AND MANAGEMENT METHOD THEREOF Public/Granted day:2023-05-11
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