Invention Grant
- Patent Title: Decoder circuit including decoders with respective performance and power levels and decoding respective subsets of codewords of received data
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Application No.: US17882136Application Date: 2022-08-05
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Publication No.: US11863204B2Publication Date: 2024-01-02
- Inventor: Mario A. Castrillon , Damián A. Morero , Genaro Bergero , Cristian Cavenio , Teodoro Goette , Martin Asinari , Ramiro R. Lopez , Mario R. Hueda
- Applicant: Marvell Asia Pte Ltd.
- Applicant Address: SG Singapore
- Assignee: Marvell Asia Pte Ltd.
- Current Assignee: Marvell Asia Pte Ltd.
- Current Assignee Address: SG Singapore
- Main IPC: H03M13/37
- IPC: H03M13/37 ; H03M13/11 ; H03M13/01 ; H03M13/00

Abstract:
A decoder circuit includes first and second decoders. The first decoder is a first type of decoder configured to receive data encoded with an error correction code and decode and eliminate errors from a first subset of codewords of the data. The second decoder is a second type of decoder configured receive the data encoded with the error correction code and decode and eliminate errors from a second subset of codewords of the data, different from the first subset of the codewords, without attempting to decode and eliminate errors from the first subset of the codewords.
Public/Granted literature
- US20220385310A1 METHOD AND DEVICE FOR ENERGY-EFFICIENT DECODERS Public/Granted day:2022-12-01
Information query
IPC分类: