Invention Grant
- Patent Title: Combining voltage ramps to create linear voltage ramp
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Application No.: US17938745Application Date: 2022-10-07
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Publication No.: US11863191B2Publication Date: 2024-01-02
- Inventor: Joseph H. Colles , Steven E. Rosenbaum
- Applicant: Silanna Asia Pte Ltd
- Applicant Address: SG Singapore
- Assignee: Silanna Asia Pte Ltd
- Current Assignee: Silanna Asia Pte Ltd
- Current Assignee Address: SG Singapore
- Agency: MLO, a professional corp.
- Main IPC: H03K4/50
- IPC: H03K4/50 ; H03K7/08

Abstract:
An improved ramp generator enables a very high degree of linearity in an output voltage ramp signal. Output ramps of the output voltage ramp signal are alternatingly produced from two preliminary ramp signals during alternating time periods. Preliminary ramps are produced at different preliminary ramp nodes that are alternatingly connected to an output node. The preliminary ramps continuously ramp during and in some cases beyond, e.g., before and/or after, the time periods. In some embodiments, switches alternatingly connect two capacitors to at least one current source, a reset voltage source, and the output node to alternatingly produce the preliminary ramps.
Public/Granted literature
- US20230034405A1 COMBINING VOLTAGE RAMPS TO CREATE LINEAR VOLTAGE RAMP Public/Granted day:2023-02-02
Information query
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