Circuits, methods, and systems for generating data outputs based on sampled data inputs. One circuit includes a first clock-activated transistor electrically coupled to a first shared clock node, a second clock-activated transistor coupled to a second shared clock node, a third clock-activated transistor coupled to a third shared clock node, a plurality of flip-flops, a latch electrically coupled to the second shared clock node and the third shared clock node, and a first keeper sub-circuit electrically coupled to the third shared clock node and at least one of a first output or a second output of the latch. Each flip-flop of the plurality of flip-flops includes a latch electrically coupled to the second shared clock node and the third shared clock node and a first keeper sub-circuit electrically coupled to the third shared clock node and at least one of a first output or a second output of the latch.