Invention Grant
- Patent Title: Bias circuit
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Application No.: US17328473Application Date: 2021-05-24
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Publication No.: US11863129B2Publication Date: 2024-01-02
- Inventor: Hideyo Yamashiro
- Applicant: Murata Manufacturing Co., Ltd.
- Applicant Address: JP Kyoto
- Assignee: MURATA MANUFACTURING CO., LTD.
- Current Assignee: MURATA MANUFACTURING CO., LTD.
- Current Assignee Address: JP Kyoto
- Agency: Pearne & Gordon LLP
- Priority: JP 20090842 2020.05.25
- Main IPC: H03F1/30
- IPC: H03F1/30 ; H03F3/21

Abstract:
A bias circuit includes first to sixth transistors and first to fifth resistors. The collector of the fifth transistor is coupled to a node in a path connecting the collector of the fourth transistor and one end of the third resistor. The collector of the sixth transistor Tr6 is coupled to one end of the fifth resistor.
Public/Granted literature
- US20210367561A1 BIAS CIRCUIT Public/Granted day:2021-11-25
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