Invention Grant
- Patent Title: Nanostructure with various widths
-
Application No.: US17837927Application Date: 2022-06-10
-
Publication No.: US11862634B2Publication Date: 2024-01-02
- Inventor: Hsiao-Han Liu , Chih-Hao Wang , Kuo-Cheng Chiang , Shi-Ning Ju , Kuan-Lun Cheng
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Birch, Stewart, Kolasch & Birch, LLP
- The original application number of the division: US16911665 2020.06.25
- Main IPC: H01L27/088
- IPC: H01L27/088 ; H01L21/8234 ; H01L29/78

Abstract:
A semiconductor structures and a method for forming the same are provided. The semiconductor structure includes first silicon-containing layers, second silicon-containing layers, third silicon-containing layers, and fourth silicon-containing layers vertically suspended over a substrate and laterally spaced apart from each other. In addition, the first silicon-containing layers and the second silicon-containing layers are narrower than the third silicon-containing layers and the fourth silicon-containing layers. The semiconductor structure further includes first source/drain features, second source/drain features, third source/drain features, and fourth source/drain features attaching to opposite sides of the first silicon-containing layers, the second silicon-containing layers, the third silicon-containing layers, and the fourth silicon-containing layers, respectively. In addition, the first source/drain features are merged with the second source/drain features while the third source/drain features are spaced apart from the fourth source/drain features.
Public/Granted literature
- US20220310453A1 NANOSTRUCTURE WITH VARIOUS WIDTHS Public/Granted day:2022-09-29
Information query
IPC分类: