Invention Grant
- Patent Title: Integrated circuit layout including standard cells of different gate line widths and same gate line pitch
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Application No.: US17348784Application Date: 2021-06-16
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Publication No.: US11862622B2Publication Date: 2024-01-02
- Inventor: Kun-Yuan Wu , Wei-Jen Wang , Chien-Fu Chen , Chen-Hsien Hsu , Chien-Hung Chen , Chun-Hsien Lin
- Applicant: UNITED MICROELECTRONICS CORP.
- Applicant Address: TW Hsin-Chu
- Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee Address: TW Hsin-Chu
- Agent Winston Hsu
- Priority: CN 2110453740.0 2021.04.26
- Main IPC: H01L27/02
- IPC: H01L27/02 ; H03K19/20

Abstract:
An integrated circuit layout includes a first standard cell and a second standard cell. The first standard cell includes first gate lines arranged along a first direction and extending along a second direction. The second standard cell abuts to one side of the first standard cell along the second direction and includes second gate lines arranged along the first direction and extending along the second direction. A first gate line width of the first gate lines and a second gate line width of the second gate lines are different. A first cell width of the first standard cell and a second cell width of the second standard cell are integral multiples of a default gate line pitch of the first gate lines and the second gate lines. At least some of the second gate lines and at least some of the first gate lines are aligned along the second direction.
Public/Granted literature
- US20220344321A1 INTEGRATED CIRCUIT LAYOUT Public/Granted day:2022-10-27
Information query
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