Invention Grant
- Patent Title: Scalable architecture for reduced cycles across SOC
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Application No.: US16677213Application Date: 2019-11-07
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Publication No.: US11862602B2Publication Date: 2024-01-02
- Inventor: Javier A. Delacruz , Richard E. Perego
- Applicant: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
- Applicant Address: US CA San Jose
- Assignee: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
- Current Assignee: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
- Current Assignee Address: US CA San Jose
- Agency: Knobbe, Martens, Olson & Bear LLP
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L23/00 ; H01L23/48

Abstract:
A microelectronic assembly may include a semiconductor wafer having first and second surfaces extending in first and second directions, the semiconductor wafer having network nodes connected to one another via local adjacent connections each extending in only one of the first and second directions, and an interconnection structure comprising a low-loss dielectric material and having first and second opposite surfaces extending in third and fourth directions each oriented at an oblique angle relative to the first and second directions, the interconnection structure having local oblique connections each extending in only one of the third and fourth directions. The semiconductor wafer may be directly bonded to the interconnection structure such that each of the network nodes is connected with at least one of the other network nodes, without use of conductive bonding material, through at least one of the local adjacent connections and at least one of the local oblique connections.
Public/Granted literature
- US20210143125A1 Scalable Architecture for Reduced Cycles Across SoC Public/Granted day:2021-05-13
Information query
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