Invention Grant
- Patent Title: Testing method for packaged chip, testing system for packaged chip, computer device and storage medium
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Application No.: US17615566Application Date: 2021-05-17
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Publication No.: US11862269B2Publication Date: 2024-01-02
- Inventor: Cheng-Jer Yang
- Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
- Applicant Address: CN Hefei
- Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
- Current Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
- Current Assignee Address: CN Hefei
- Agency: Syncoda LLC
- Agent Feng Ma
- Priority: CN 2010689689.9 2020.07.17
- International Application: PCT/CN2021/094113 2021.05.17
- International Announcement: WO2022/012147A 2022.01.20
- Date entered country: 2021-11-30
- Main IPC: G11C29/10
- IPC: G11C29/10 ; G11C29/12

Abstract:
A testing method for a packaged chip includes: acquiring a target chip; in the post-burn-in test process, testing a first data retention time of each memory unit on the target chip; comparing the first data retention time of each memory unit with a preset reference time; and, determining that the target chip is a qualified chip if the first data retention time of each memory unit is not less than the preset reference time. In the present application, by testing the first data retention time of each memory unit on the target chip in the post-burn-in test process, it is determined that the target chip is a qualified chip if the first data retention time of each memory unit is not less than the preset reference time.
Public/Granted literature
- US20230187005A1 TESTING METHOD FOR PACKAGED CHIP, TESTING SYSTEM FOR PACKAGED CHIP, COMPUTER DEVICE AND STORAGE MEDIUM Public/Granted day:2023-06-15
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