A memory cell includes a write bit line, a read word line, a write transistor, and a read transistor. The write transistor is coupled between the write bit line and a first node. The read transistor is coupled to the write transistor by the first node. The read transistor includes a ferroelectric layer, a drain terminal of the read transistor is coupled to the read word line, and a source terminal of the read transistor is coupled to a second node. The write transistor is configured to set a stored data value of the memory cell by a write bit line signal that adjusts a polarization state of the read transistor. The polarization state corresponds to the stored data value.