Invention Grant
- Patent Title: 3D RRAM cell structure for reducing forming and set voltages
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Application No.: US17392760Application Date: 2021-08-03
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Publication No.: US11751406B2Publication Date: 2023-09-05
- Inventor: Te-Hsien Hsieh , Tzu-Yu Chen , Kuo-Chi Tu , Yuan-Tai Tseng
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L27/24
- IPC: H01L27/24 ; H01L45/00 ; G11C13/00 ; H10B63/00 ; H10N70/00

Abstract:
An RRAM cell stack is formed over an opening in a dielectric layer. The dielectric layer is sufficiently thick and the opening is sufficiently deep that an RRAM cell can be formed by a planarization process. The resulting RRAM cells may have a U-shaped profile. The RRAM cell area includes contributions from a bottom portion in which the RRAM cell layers are stacked parallel to the substrate and a side portion in which RRAM cell layers are stacked roughly perpendicular to the substrate. The combined side and bottom portions of the curved RRAM cell provide an increased area in comparison to a planar cell stack. The increased area lowers forming and set voltages for the RRAM cell.
Public/Granted literature
- US20210366987A1 3D RRAM CELL STRUCTURE FOR REDUCING FORMING AND SET VOLTAGES Public/Granted day:2021-11-25
Information query
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