Invention Grant
- Patent Title: Method of producing wiring board that includes dual-layered insulating film
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Application No.: US17547576Application Date: 2021-12-10
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Publication No.: US11751340B2Publication Date: 2023-09-05
- Inventor: Akitoshi Sakaue
- Applicant: JAPAN AVIATION ELECTRONICS INDUSTRY, LIMITED
- Applicant Address: JP Tokyo
- Assignee: JAPAN AVIATION ELECTRONICS INDUSTRY, LIMITED
- Current Assignee: JAPAN AVIATION ELECTRONICS INDUSTRY, LIMITED
- Current Assignee Address: JP Tokyo
- Agency: GREENBLUM & BERNSTEIN, P.L.C.
- Priority: JP 21001224 2021.01.07
- Main IPC: H05K3/46
- IPC: H05K3/46 ; H05K1/02 ; H05K3/10

Abstract:
A wiring board includes a conductor pattern formed on a board, and an insulating film that covers at least part of the conductor pattern. A first insulating film is provided in a first region on the board, the first region covering at least part of the conductor pattern and having a first border segment. A second insulating film is provided in a second region on the board, the second region covering at least part of the first region and having a second border segment. The second border segment is located outside the first region, and the shortest distance from any point belonging to the second border segment to the first border segment is not more than 400 μm.
Public/Granted literature
- US20220217850A1 PRODUCTION METHOD OF WIRING BOARD AND WIRING BOARD Public/Granted day:2022-07-07
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