An IC includes a first set of core logic configured to convert data between a single stream and a double stream, and a first data I/O block on a first side of the first set of core logic. The first data I/O block interfaces with the first set of core logic and a DRAM. The IC further includes a second set of core logic configured to process CA information, and a first CA I/O subblock on a second side of the first set of core logic. The first CA I/O subblock interfaces with the second set of core logic and the DRAM. The IC further includes a first set of power switches adjacent at least one side of the first CA I/O subblock. The first set of power switches is coupled to the first set of core logic and the second set of core logic.