Invention Grant
- Patent Title: Flip-flop with input and output select and output masking that enables low power scan for retention
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Application No.: US17517054Application Date: 2021-11-02
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Publication No.: US11750178B2Publication Date: 2023-09-05
- Inventor: Thomas Saroshan David
- Applicant: Silicon Laboratories Inc.
- Applicant Address: US TX Austin
- Assignee: Silicon Laboratories Inc.
- Current Assignee: Silicon Laboratories Inc.
- Current Assignee Address: US TX Austin
- Agency: Huffman Law Group, PC
- Agent Gary Stanford
- Main IPC: H03K3/356
- IPC: H03K3/356 ; H03K3/012 ; H03K3/037

Abstract:
A flip-flop including a scan enable input for receiving a scan enable signal, a clock input for receiving a clock signal, input select circuitry that is configured to select between a data input and a scan input based on a state of the scan enable signal for providing a selected input, latching circuitry that is configured to latch the selected input to a preliminary output node in response to transitions of the clock signal, and output select circuitry that is configured to provide a state of the preliminary output node to a selected one of a scan output and a data output based on a state of the scan enable signal. The flip-flop may be implemented using fast yet leaky transistors. The data output may be disabled to prevent toggling other circuitry when scanning into or out of a memory for data retention.
Public/Granted literature
- US20230133269A1 FLIP-FLOP WITH INPUT AND OUTPUT SELECT AND OUTPUT MASKING THAT ENABLES LOW POWER SCAN FOR RETENTION Public/Granted day:2023-05-04
Information query
IPC分类: