Invention Grant
- Patent Title: Selective dual silicide formation using a maskless fabrication process flow
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Application No.: US17306511Application Date: 2021-05-03
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Publication No.: US11749682B2Publication Date: 2023-09-05
- Inventor: Mrunal A. Khaderbad , Pang-Yen Tsai , Yasutoshi Okuno
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: HAYNES AND BOONE, LLP
- The original application number of the division: US16454871 2019.06.27
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L21/8238 ; H01L29/45

Abstract:
A first dielectric layer is selectively formed such that the first dielectric layer is formed over a source/drain region of a first type of transistor but not over a source/drain region of a second type of transistor. The first type of transistor and the second type of transistor have different types of conductivity. A first silicide layer is selectively formed such that the first silicide layer is formed over the source/drain region of the second type of transistor but not over the source/drain region of the first type of transistor. The first dielectric layer is removed. A second silicide layer is formed over the source/drain region of the first type of transistor.
Public/Granted literature
- US20210257262A1 Selective Dual Silicide Formation Using A Maskless Fabrication Process Flow Public/Granted day:2021-08-19
Information query
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