A memory includes: a memory core; an error correction circuit suitable for correcting, when a number of one or more errors detected in data read from the memory core is equal to or greater than a threshold value, the detected errors based on an error correction code read from the memory core to produce an error-corrected data; and a data transferring circuit suitable for: outputting, when the detected errors are corrected, the error-corrected data according to a long read latency, and outputting, when the number of the detected errors is less than the threshold value or no error is detected in the read data, the read data according to a short read latency.