Display device with reduced parasitic capacitances between pixel electrodes and data lines
Abstract:
The present disclosure relates to a display device, and the display device according to an exemplary embodiment of the present inventive concept includes: a first pixel circuit portion including at least one transistor; a second pixel circuit portion including at least one transistor; a first pixel electrode electrically connected to the first pixel circuit portion; a second pixel electrode electrically connected to the second pixel circuit portion; a first data line electrically connected to the first pixel circuit portion; and a second data line electrically connected to the second pixel circuit portion, wherein the first data line and the second data line are arranged adjacent to each other along a first direction, and the second pixel electrode overlaps the first data line and the second data line in a plan view.
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