Invention Grant
- Patent Title: Dual channel gate all around transistor device and fabrication methods thereof
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Application No.: US17805962Application Date: 2022-06-08
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Publication No.: US11721594B2Publication Date: 2023-08-08
- Inventor: Wei-Sheng Yun , Chih-Hao Wang , Jui-Chien Huang , Kuo-Cheng Chiang , Chih-Chao Chou , Chun-Hsiung Lin , Pei-Hsun Wang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L29/06 ; H01L21/02 ; H01L21/324 ; H01L29/423 ; H01L27/092 ; H01L29/08 ; H01L29/10 ; H01L21/306 ; H01L21/311 ; H01L21/027 ; H01L21/762 ; H01L29/66

Abstract:
A semiconductor structure includes a fin disposed on a substrate, the fin including a channel region comprising a plurality of channels vertically stacked over one another, the channels comprising germanium distributed therein. The semiconductor structure further includes a gate stack engaging the channel region of the fin and gate spacers disposed between the gate stack and the source and drain regions of the fin, wherein each channel of the channels includes a middle section wrapped around by the gate stack and two end sections engaged by the gate spacers, wherein a concentration of germanium in the middle section of the channel is higher than a concentration of germanium in the two end sections of the channel, and wherein the middle section of the channel further includes a core portion and an outer portion surrounding the core portion with a germanium concentration profile from the core portion to the outer portion.
Public/Granted literature
- US20220301943A1 Dual Channel Gate All Around Transistor Device and Fabrication Methods Thereof Public/Granted day:2022-09-22
Information query
IPC分类: