Invention Grant
- Patent Title: Method of making vertical semiconductor nanosheets with diffusion breaks
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Application No.: US17480318Application Date: 2021-09-21
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Publication No.: US11721592B2Publication Date: 2023-08-08
- Inventor: Mark I. Gardner , H. Jim Fulford
- Applicant: Tokyo Electron Limited
- Applicant Address: JP Tokyo
- Assignee: Tokyo Electron Limited
- Current Assignee: Tokyo Electron Limited
- Current Assignee Address: JP Tokyo
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L29/06 ; H01L29/78 ; H01L29/66 ; H01L21/8238 ; H01L29/423 ; H01L29/417

Abstract:
A method of microfabrication includes providing a substrate having a first layer including a first semiconductor material. A second layer of a second semiconductor material is formed over the first layer. The second layer is directionally etched using a mask to form independent core structures of the second semiconductor material on the first semiconductor material. A third layer of a first dielectric material is formed on an exposed surface of the first layer to cover a lower portion of a respective sidewall of each core structure. A shell structure is formed on an upper portion of a respective sidewall of each core structure to form shell structures including at least one semiconductor material. The core structures are removed such that each shell structure forms a vertical semiconductor structure extending vertically from the first layer and electrically isolated from the first semiconductor material by the first dielectric material.
Public/Granted literature
- US20220254689A1 METHOD OF MAKING VERTICAL SEMICONDUCTOR NANOSHEETS WITH DIFFUSION BREAKS Public/Granted day:2022-08-11
Information query
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