- Patent Title: Semiconductor memory device including separated epitaxial layers
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Application No.: US16805447Application Date: 2020-02-28
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Publication No.: US11672121B2Publication Date: 2023-06-06
- Inventor: Tadashi Yamaguchi
- Applicant: RENESAS ELECTRONICS CORPORATION
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: McDermott Will & Emery LLP
- Priority: JP 2019037315 2019.03.01
- Main IPC: H01L27/11568
- IPC: H01L27/11568 ; H01L27/11573 ; H01L29/45 ; H01L29/66 ; H01L29/792 ; H01L21/285 ; H01L29/78

Abstract:
In a semiconductor device having MONOS memories configured by fin-type MISFETs, an increase in parasitic capacitance between wirings accompanying miniaturization of the semiconductor device is prevented, and the reliability of the semiconductor device is improved. In a memory cell array in which a plurality of MONOS type memory cells formed on fins are arranged, source regions formed on the plurality of fins arranged in a short direction of the fin are electrically connected to each other by one epitaxial layer straddling the fins.
Public/Granted literature
- US20200279856A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME Public/Granted day:2020-09-03
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