Invention Grant
- Patent Title: Stacked semiconductor package and packaging method thereof
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Application No.: US17210452Application Date: 2021-03-23
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Publication No.: US11670622B2Publication Date: 2023-06-06
- Inventor: Yin-Huang Kung , Chia-Hung Lin , Fu-Yuan Yao , Chun-Wu Liu
- Applicant: Powertech Technology Inc.
- Applicant Address: TW Hukou Township, Hsinchu County
- Assignee: Powertech Technology Inc.
- Current Assignee: Powertech Technology Inc.
- Current Assignee Address: TW Hukou Township
- Agency: patenttm.us
- Priority: TW 9140719 2020.11.20
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L25/00

Abstract:
A stacked semiconductor package has a substrate, a first chip, at least one spacer, a second chip and an encapsulation. The first chip and the second chip are intersecting stacked on the substrate. The at least one spacer is stacked on the substrate to support the second chip. The encapsulation is formed to encapsulate the substrate, the first chip, the at least one spacer and the second chip. The at least one spacer is made of the material of the encapsulation. Therefore, the adhesion between the at least one spacer and the encapsulation is enhanced to avoid the delamination during the reliability test and enhances the reliability of the stacked semiconductor package.
Public/Granted literature
- US20220165709A1 STACKED SEMICONDUCTOR PACKAGE AND PACKAGING METHOD THEREOF Public/Granted day:2022-05-26
Information query
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