Invention Grant
- Patent Title: Stacking via structures for stress reduction
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Application No.: US17126957Application Date: 2020-12-18
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Publication No.: US11670601B2Publication Date: 2023-06-06
- Inventor: Shu-Shen Yeh , Che-Chia Yang , Chin-Hua Wang , Po-Yao Lin , Shin-Puu Jeng , Chia-Hsiang Lin
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/31 ; H01L21/48 ; H01L21/56 ; H01L23/538 ; H01L23/48 ; H01L25/065

Abstract:
A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.
Public/Granted literature
- US20220020700A1 Stacking Via Structures for Stress Reduction Public/Granted day:2022-01-20
Information query
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