Invention Grant
- Patent Title: Adaptive gate-bias regulator for output buffer with power-supply voltage above core power-supply voltage
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Application No.: US17876750Application Date: 2022-07-29
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Publication No.: US11646737B1Publication Date: 2023-05-09
- Inventor: Chit Sang Chan , Chun-Kit Yam
- Applicant: Hong Kong Applied Science and Technology Research Institute Company Limited
- Applicant Address: HK Hong Kong
- Assignee: Hong Kong Applied Science and Technology Research Institute Company Limited
- Current Assignee: Hong Kong Applied Science and Technology Research Institute Company Limited
- Current Assignee Address: HK Hong Kong
- Agency: gPatent LLC
- Agent Stuart T. Auvinen
- Main IPC: H03K3/00
- IPC: H03K3/00 ; H03K3/16 ; H03K5/24 ; H03K17/687 ; H03K19/0185 ; H03K17/10 ; H03K19/003

Abstract:
A level-shifting output buffer has cascode transistors with varying rather than fixed gate bias voltages. An adaptive regulator bypasses the I/O pad voltage to a regulator output when the I/O begins switching, but later clamps the regulator output to a middle bias voltage. The regulator output can be applied to a supply terminal of a buffer that drives the gate of the cascode transistor. Since the adaptive regulator follows the I/O pad voltage as switching begins, a voltage boost is provided to the gates of the cascode transistors, allowing for higher currents or smaller cascode transistors and preventing over-voltage stress. The adaptive regulator has an n-channel bypass transistor between the I/O pad and the regulator output, and an n-channel clamp transistor between the regulator output and the middle bias, with a gate driven from the I/O pad by either a p-channel gate-biasing transistor or an n-channel gate-biasing transistor.
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