Invention Grant
- Patent Title: Method of manufacturing a semiconductor package including a first sub-package stacked atop a second sub-package
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Application No.: US17643593Application Date: 2021-12-10
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Publication No.: US11646299B2Publication Date: 2023-05-09
- Inventor: Shing-Yih Shih
- Applicant: NANYA TECHNOLOGY CORPORATION
- Applicant Address: TW New Taipei
- Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee Address: TW New Taipei
- Agency: CKC & Partners Co., LLC
- The original application number of the division: US16833690 2020.03.30
- Main IPC: H01L25/10
- IPC: H01L25/10 ; H01L23/48 ; H01L21/56 ; H01L21/768 ; H01L23/00 ; H01L25/00

Abstract:
A semiconductor package includes a first sub-package and a second sub-package. The first sub-package is stacked atop the second sub-package. Each of the first sub-package and the second sub-package includes at least two first semiconductor dies, a second semiconductor die, a plurality of molding pieces, a bond-pad layer, a plurality of redistribution layers (RDLs) and a plurality of bumps. The bumps of the first sub-package are attached to the bond-pad layer of the second sub-package.
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Information query
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