Invention Grant
- Patent Title: Collapsing of multiple nested loops, methods, and instructions
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Application No.: US17323409Application Date: 2021-05-18
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Publication No.: US11640298B2Publication Date: 2023-05-02
- Inventor: Mikhail Plotnikov , Andrey Naraikin , Elmoustapha Ould-Ahmed-Vall
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F9/32

Abstract:
In an embodiment, the present invention is directed to a processor including a decode logic to receive a multi-dimensional loop counter update instruction and to decode the multi-dimensional loop counter update instruction into at least one decoded instruction, and an execution logic to execute the at least one decoded instruction to update at least one loop counter value of a first operand associated with the multi-dimensional loop counter update instruction by a first amount. Methods to collapse loops using such instructions are also disclosed. Other embodiments are described and claimed.
Public/Granted literature
- US20210279061A1 COLLAPSING OF MULTIPLE NESTED LOOPS, METHODS, AND INSTRUCTIONS Public/Granted day:2021-09-09
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