Invention Grant
- Patent Title: Signal output circuit and circuit for outputting delayed signal
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Application No.: US17668756Application Date: 2022-02-10
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Publication No.: US11621707B2Publication Date: 2023-04-04
- Inventor: Jia Wang
- Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
- Applicant Address: CN Hefei
- Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
- Current Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
- Current Assignee Address: CN Hefei
- Agency: Cooper Legal Group, LLC
- Priority: CN202110256939.4 20210309
- Main IPC: H03K5/15
- IPC: H03K5/15 ; H03K5/1534 ; H03K5/13

Abstract:
A signal output circuit and a circuit for outputting a delayed signal are provided. The signal output circuit includes: a first control subcircuit, configured to receive a first pulse signal and an input signal and output a first adjustment signal, a first preset edge of the first adjustment signal has a first delay relative to a rising edge of the input signal; a second control subcircuit configured to receive a second pulse signal and the input signal and output a second adjustment signal; and the signal output subcircuit is configured to receive the first adjustment signal and the second adjustment signal, and output a delayed output signal, a rising edge of the delayed output signal is generated according to the first preset edge of the first adjustment signal, and a falling edge of the delayed output signal is generated according to the second preset edge of the second adjustment signal.
Public/Granted literature
- US20220294438A1 SIGNAL OUTPUT CIRCUIT AND CIRCUIT FOR OUTPUTTING DELAYED SIGNAL Public/Granted day:2022-09-15
Information query
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