Invention Grant
- Patent Title: Method for fabricating semiconductor device with self-aligned landing pad
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Application No.: US17380745Application Date: 2021-07-20
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Publication No.: US11621265B2Publication Date: 2023-04-04
- Inventor: Te-Yin Chen
- Applicant: NANYA TECHNOLOGY CORPORATION
- Applicant Address: TW New Taipei
- Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee Address: TW New Taipei
- Agency: Muncy, Geissler, Olds & Lowe, P.C.
- Main IPC: H10B12/00
- IPC: H10B12/00 ; H01L21/768 ; H01L27/108

Abstract:
The present application discloses a method for fabricating a semiconductor device with a self-aligned landing pad. The method includes: providing a substrate; forming a dielectric layer with a plug over the substrate; performing an etching process to remove a portion of the dielectric layer to expose a protruding portion of the plug; forming a liner layer covering the dielectric layer and the protruding portion; and performing a thermal process to form a landing pad over the dielectric layer. The landing pad comprises a protruding portion of the plug, a first silicide layer disposed over the protruding portion, and a second silicide layer disposed on a sidewall of the protruding portion.
Public/Granted literature
- US20210351187A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH SELF-ALIGNED LANDING PAD Public/Granted day:2021-11-11
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