A memory circuit includes a first word line, a first and second bit line, a first and second inverter, a P-type pass gate transistor and a pre-charge circuit. The first word line extends in a first direction. The first and second bit line extend in a second direction. The first inverter has a first storage node coupled to the second inverter. The second inverter has a second storage node coupled to the first inverter, and is not coupled to the second bit line. The P-type pass gate transistor is coupled between the first storage node and the first bit line. The pre-charge circuit is coupled to the first or second bit line, and is configured to charge the first or second bit line to a pre-charge voltage responsive to a first signal. The pre-charge voltage is between a voltage of a first logical level and a second logical level.