Invention Grant
- Patent Title: Simultaneous bonding approach for high quality wafer stacking applications
-
Application No.: US17371537Application Date: 2021-07-09
-
Publication No.: US11621186B2Publication Date: 2023-04-04
- Inventor: Xin-Hua Huang , Ping-Yin Liu , Chang-Chen Tsao
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L21/68
- IPC: H01L21/68 ; H01L21/683 ; H01L21/18 ; H01L21/687

Abstract:
In some embodiments, the present disclosure relates to a method that includes aligned a first wafer with a second wafer. The second wafer is spaced apart from the first wafer. The first wafer is arranged on a first electrostatic chuck (ESC). The first ESC has electrostatic contacts that are configured to attract the first wafer to the first ESC. Further, the second wafer is brought toward the first wafer to directly contact the first wafer at an inter-wafer interface. The inter-wafer interface is localized to a center of the first wafer. The second wafer is deformed to gradually expand the inter-wafer interface from the center of the first wafer toward an edge of the first wafer. The electrostatic contacts of the first ESC are turned OFF such that the first and second wafers are bonded to one another by the inter-wafer interface.
Public/Granted literature
- US20210335646A1 SIMULTANEOUS BONDING APPROACH FOR HIGH QUALITY WAFER STACKING APPLICATIONS Public/Granted day:2021-10-28
Information query
IPC分类: