Invention Grant
- Patent Title: EFuse circuit, method, layout, and structure
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Application No.: US17541245Application Date: 2021-12-02
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Publication No.: US11621046B2Publication Date: 2023-04-04
- Inventor: Meng-Sheng Chang , Yao-Jen Yang
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Hauptman Ham, LLP
- Main IPC: G11C17/16
- IPC: G11C17/16 ; G06F30/392 ; G11C17/18 ; H01L23/525 ; H01L27/02 ; H01L27/112 ; G06F119/18

Abstract:
An IC structure includes a bit line extending in a first direction, first and second pluralities of FinFETs, and a plurality of eFuses. The FinFETs of the first plurality of FinFETs alternate with the FinFETs of the second plurality of FinFETs along the bit line, each eFuse of the plurality of eFuses includes a conductive segment extending between first and second contact regions, the first contact region is electrically connected to the bit line, and the second contact region is electrically connected to each of an adjacent FinFET of the first plurality of FinFETs and an adjacent FinFET of the second plurality of FinFETs.
Public/Granted literature
- US20220093196A1 EFUSE CIRCUIT, METHOD, LAYOUT, AND STRUCTURE Public/Granted day:2022-03-24
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