Invention Grant
- Patent Title: Using multi-tiered cache to satisfy input/output requests
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Application No.: US17494680Application Date: 2021-10-05
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Publication No.: US11620218B2Publication Date: 2023-04-04
- Inventor: Lokesh Mohan Gupta , Edward Hsiu-Wei Lin , Beth Ann Peterson , Matthew G. Borlick
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Zilka-Kotab, P.C.
- Main IPC: G06F12/0802
- IPC: G06F12/0802 ; G06F3/06

Abstract:
A computer-implemented method, according to one approach, includes: determining whether to satisfy an I/O request using a first tier of memory in a secondary cache by inspecting a bypass indication in response to determining that the input/output (I/O) request includes a bypass indication. The secondary cache is coupled to a primary cache and a data storage device. The secondary cache also includes the first tier of memory and a second tier of memory. Moreover, in response to determining to satisfy the I/O request using the first tier of memory in the secondary cache, the I/O request is satisfied using the first tier of memory in the secondary cache. The updated data is also destaged from the secondary cache to the data storage device in response to determining that data associated with the I/O request has been updated as the result of satisfying the I/O request using the secondary cache.
Public/Granted literature
- US20220027267A1 USING MULTI-TIERED CACHE TO SATISFY INPUT/OUTPUT REQUESTS Public/Granted day:2022-01-27
Information query
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