Memory management method, memory control circuit unit and memory storage apparatus
Abstract:
A memory management method, a memory control circuit unit and a memory storage apparatus are provided. The method includes: recording a valid count of each physical erasing unit in a plurality of physical erasing units; sequentially arranging M physical erasing units corresponding to each of chip enable groups according to the valid count to form a plurality of sorted physical erasing units; remapping the physical erasing units corresponding to M virtual blocks according to the plurality of sorted physical erasing units; calculating a total number of valid counts of the remapped M virtual blocks, and sequentially arranging the remapped M virtual blocks according to the total number of valid counts to form a plurality of sorted virtual blocks; and sequentially extracting at least one of the sorted virtual blocks as a source virtual block to perform a garbage collection operation.
Information query
Patent Agency Ranking
0/0