Invention Grant
- Patent Title: Wafer placement table and method for manufacturing the same
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Application No.: US16898772Application Date: 2020-06-11
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Publication No.: US11602012B2Publication Date: 2023-03-07
- Inventor: Yutaka Unno , Shuichiro Motoyama
- Applicant: NGK INSULATORS, LTD.
- Applicant Address: JP Nagoya
- Assignee: NGK INSULATORS, LTD.
- Current Assignee: NGK INSULATORS, LTD.
- Current Assignee Address: JP Nagoya
- Agency: Burr Patent Law, PLLC
- Priority: JPJP2019-122749 20190701
- Main IPC: H05B3/68
- IPC: H05B3/68 ; H05B1/02 ; H05B3/74 ; H05B3/28

Abstract:
A wafer placement table includes: a ceramic member having a wafer placement surface; a mesh electrode buried in the ceramic member; a conductive connection member in contact with the mesh electrode and exposed to outside from a surface of the ceramic member on the opposite side of the wafer placement surface; and an external current-carrying member joined to a surface of the connection member exposed to outside. The mesh electrode has a mesh opening in a region that faces the connection member, and the mesh opening is filled with a sintered conductor being a sintered body of a mixture containing a conductive powder and a ceramic raw material.
Public/Granted literature
- US20210007181A1 WAFER PLACEMENT TABLE AND METHOD FOR MANUFACTURING THE SAME Public/Granted day:2021-01-07
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