Zero knowledge proof hardware accelerator and the method thereof
Abstract:
A hardware accelerator for accelerating the zero knowledge succinct non-interactive argument of knowledge (zk-SNARK) protocol by reducing the computation time of the cryptographic verification is disclosed. The accelerator includes a zk-SNARK engine having one or more processing units running in parallel. The processing unit can include one or more multiply-accumulate operation (MAC) units, one or more fast Fourier transform (FFT) units; and one or more elliptic curve processor (ECP) units. The one or more ECP units are configured to reduce a bit-length of a scalar di in an ECP algorithm used for generating a proof, thereby the cryptographic verification requires less computation power.
Public/Granted literature
Information query
Patent Agency Ranking
0/0