Invention Grant
- Patent Title: Amplifier biasing techniques
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Application No.: US16562702Application Date: 2019-09-06
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Publication No.: US11545936B2Publication Date: 2023-01-03
- Inventor: Lawrence Howard Edelson
- Applicant: Analog Devices, Inc.
- Applicant Address: US MA Norwood
- Assignee: Analog Devices, Inc.
- Current Assignee: Analog Devices, Inc.
- Current Assignee Address: US MA Norwood
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: H03F1/02
- IPC: H03F1/02 ; H03F3/26

Abstract:
Techniques for biasing output transistor of a push-pull amplifier output stage are provided. In certain applications the techniques can improve efficiency of the amplifier. In an example, a circuit can include an output stage including first and second output transistors, a first scaled replica transistor corresponding to the first output transistor, and an amplifier circuit in a feedback arrangement for biasing a gate of the first output transistor at a level that, at a specified stand-by current level of the first output transistor, reproduces a voltage difference between the drain and source terminals of the first output transistor across the drain and source terminals of the first replica transistor.
Public/Granted literature
- US20210075370A1 AMPLIFER BIASING TECHNIQUES Public/Granted day:2021-03-11
Information query
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