Invention Grant
- Patent Title: Semiconductor structure and method for forming the same
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Application No.: US17104218Application Date: 2020-11-25
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Publication No.: US11545552B2Publication Date: 2023-01-03
- Inventor: Nan Wang
- Applicant: Semiconductor Manufacturing International (Shanghai) Corporation , Semiconductor Manufacturing International (Beijing) Corporation
- Applicant Address: CN Shanghai; CN Beijing
- Assignee: Semiconductor Manufacturing International (Shanghai) Corporation,Semiconductor Manufacturing International (Beijing) Corporation
- Current Assignee: Semiconductor Manufacturing International (Shanghai) Corporation,Semiconductor Manufacturing International (Beijing) Corporation
- Current Assignee Address: CN Shanghai; CN Beijing
- Agency: Crowell & Moring, L.L.P.
- Priority: CN202010725785.4 20200724
- Main IPC: H01L29/417
- IPC: H01L29/417 ; H01L21/033 ; H01L29/66 ; H01L29/06 ; H01L29/40

Abstract:
A semiconductor structure and a method for forming the same are provided. One form of a forming method includes: providing a base, the base including a device region and a dummy device region, the base including an isolation layer, gate structures located on the isolation layer, a first mask layer located on the gate structures, a source-drain plug located between the gate structures and on the isolation layer, and a second mask layer located on the source-drain plug. In implementations of the present disclosure, the first mask layer and the second mask layer on the dummy device region are separately removed. Correspondingly, the first opening and the second opening respectively expose the gate structures and the source-drain plug in the dummy device region. The gate structures exposed by the first opening and the source-drain plug exposed by the second opening are removed in the same step. The gate groove at the bottom of the first opening and the source-drain groove at the bottom of the second opening are formed at the same time. Correspondingly, a dielectric layer may be formed in the gate groove and the source-drain groove in the same step. The dielectric layer may block the gate structures and the source-drain plug at the same time. This is advantageous for simplifying the formation process of the semiconductor structure.
Public/Granted literature
- US20220028990A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME Public/Granted day:2022-01-27
Information query
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