Invention Grant
- Patent Title: Semiconductor package and manufacturing method thereof
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Application No.: US17319119Application Date: 2021-05-13
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Publication No.: US11545469B2Publication Date: 2023-01-03
- Inventor: Yi-Chung Liang
- Applicant: Powerchip Semiconductor Manufacturing Corporation
- Applicant Address: TW Hsinchu
- Assignee: Powerchip Semiconductor Manufacturing Corporation
- Current Assignee: Powerchip Semiconductor Manufacturing Corporation
- Current Assignee Address: TW Hsinchu
- Agency: JCIPRNET
- Priority: TW110109889 20210319
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L23/00 ; H01L23/538 ; H01L23/532 ; H01L23/29 ; H01L23/31

Abstract:
A semiconductor package including a chip stack structure, a redistribution layer (RDL) structure and conductive plugs is provided. The chip stack structure includes stacked chips. Each of the chips includes a pad. The pads on the chips are located on the same side of the chip stack structure. The RDL structure is disposed on the first sidewall of the chip stack structure and adjacent to the pads. The conductive plugs penetrate through the RDL structure. The conductive plug is connected to the corresponding pad.
Public/Granted literature
- US20220302082A1 SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF Public/Granted day:2022-09-22
Information query
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