Invention Grant
- Patent Title: Semiconductor device bonding area including fused solder film and manufacturing method
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Application No.: US17137657Application Date: 2020-12-30
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Publication No.: US11545452B2Publication Date: 2023-01-03
- Inventor: Masanori Shindo
- Applicant: LAPIS SEMICONDUCTOR CO., LTD.
- Applicant Address: JP Kanagawa
- Assignee: LAPIS SEMICONDUCTOR CO., LTD.
- Current Assignee: LAPIS SEMICONDUCTOR CO., LTD.
- Current Assignee Address: JP Kanagawa
- Agency: Volentine, Whitt and Francos, PLLC
- Priority: JPJP2017-214885 20171107
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L21/683

Abstract:
A semiconductor device including a semiconductor substrate including an electrode; a wire connected to the electrode; a first insulating film including a first opening that partially exposes the wire; a base portion that is connected to a portion of the wire exposed via the first opening, and that includes a conductor including a recess corresponding to the first opening; and a solder film on a surface of the base portion. Solder included in the solder film is fused by a first heat treatment, and the recess is filled with the fused solder.
Public/Granted literature
- US20210118831A1 SEMICONDUCTOR DEVICE BONDING AREA INCLUDING FUSED SOLDER FILM AND MANUFACTURING METHOD Public/Granted day:2021-04-22
Information query
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