Embodiments of a marking pattern in forming the staircase structure of a three-dimensional (3D) memory device are provided. In an example, a marking pattern for controlling a trimming rate of a photoresist trimming process includes a plurality of interleaved layers, the plurality of interleaved layers including at least two layers of different materials stacking along a vertical direction over a substrate. In some embodiments, the marking pattern also includes a central marking structure that divides the marking area into a first marking sub-area farther from a device area and a second marking sub-area closer to the device area, a first pattern density of the first marking sub-area being higher than or equal to a second pattern density of the second marking sub-area.