Invention Grant
- Patent Title: Method of fabricating a semiconductor device having a liner layer with a configured profile
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Application No.: US16933541Application Date: 2020-07-20
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Publication No.: US11545390B2Publication Date: 2023-01-03
- Inventor: Joanna Chaw Yane Yin , Hua Feng Chen
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L29/66 ; H01L23/535 ; H01L29/78 ; H01L23/532 ; H01L23/485 ; H01L21/8238 ; H01L27/092 ; H01L21/285
Abstract:
Devices and methods that include for configuring a profile of a liner layer before filling an opening disposed over a semiconductor substrate. The liner layer has a first thickness at the bottom of the opening and a second thickness a top of the opening, the second thickness being smaller that the first thickness. In an embodiment, the filled opening provides a contact structure.
Public/Granted literature
- US20200350205A1 METHOD OF FABRICATING A SEMICONDUCTOR DEVICE HAVING A LINER LAYER WITH A CONFIGURED PROFILE Public/Granted day:2020-11-05
Information query
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