Invention Grant
- Patent Title: Mitigation of voltage threshold drift associated with power down condition of non-volatile memory device
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Application No.: US17165555Application Date: 2021-02-02
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Publication No.: US11545216B2Publication Date: 2023-01-03
- Inventor: Karthik Sarpatwari , Fabio Pellizzer , Jessica Chen , Nevil Gajera
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Holland & Hart LLP
- Main IPC: G11C13/00
- IPC: G11C13/00

Abstract:
Methods, systems, and devices for dirty write on power off are described. In an example, the described techniques may include writing memory cells of a device according to one or more parameters (e.g., reset current amplitude), where each memory cell is associated with a storage element storing a value based on a material property associated with the storage element. Additionally, the described techniques may include identifying, after writing the memory cells, an indication of power down for the device and refreshing, before the power down of the device, a portion of the memory cells based on identifying the indication of the power down for the device. In some cases, refreshing includes modifying at least one of the one or more parameters for a write operation for the portion of the memory cells.
Public/Granted literature
- US20210233584A1 DIRTY WRITE ON POWER OFF Public/Granted day:2021-07-29
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