Invention Grant
- Patent Title: Branch target buffer arrangement with preferential storage for unconditional branch instructions
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Application No.: US16971419Application Date: 2019-02-11
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Publication No.: US11544066B2Publication Date: 2023-01-03
- Inventor: Rakesh Kumar , Boris Grot , Vijay Nagarajan
- Applicant: The University Court of the University of Edinburgh
- Applicant Address: GB Midlothian
- Assignee: The University Court of the University of Edinburgh
- Current Assignee: The University Court of the University of Edinburgh
- Current Assignee Address: GB Midlothian
- Agency: Banner & Witcoff Ltd.
- Priority: GB1802815 20180221
- International Application: PCT/GB2019/050359 WO 20190211
- International Announcement: WO2019/162647 WO 20190829
- Main IPC: G06F9/38
- IPC: G06F9/38

Abstract:
A branch target buffer, BTB, is provided to store at least one BTB entry corresponding to a respective branch in a control flow in a sequence of machine-readable instructions of a computer program. The BTB has a tag field to compare with a program counter of a fetch address generator and at least one further field to store information characteristic of the branch instruction identified by the corresponding tag field and allowing a conditional branch to be distinguished from an unconditional branch instruction. The BTB has a predetermined storage capacity and is utilized such that unconditional branch instructions are preferentially allocated storage space in the BTB relative to conditional branch instructions.
Public/Granted literature
- US20210004233A1 BRANCH TARGET BUFFER ARRANGEMENT FOR INSTRUCTION PREFETCHING Public/Granted day:2021-01-07
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