Invention Grant
- Patent Title: Low area multiply and accumulate unit
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Application No.: US16862722Application Date: 2020-04-30
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Publication No.: US11544037B2Publication Date: 2023-01-03
- Inventor: Sudipto Chakraborty , Rajiv Joshi
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent Daniel P. Morris
- Main IPC: G06F7/544
- IPC: G06F7/544 ; G06G7/16

Abstract:
An improved electronic mixed mode multiplier and accumulate circuit for artificial intelligence and computing system applications that perform vector-vector, vector-matrix and other multiply-accumulate computations. The circuit is provided is a high resolution, high linearity, low area, low power multiply—accumulate (MAC) unit to interface with a memory device for storing computation output results. The MAC unit uses a less number of current carrying elements resulting in much lower integrated circuit area, and provides a tight matching between the current elements thus preserving inherent linearity requirements due to current mode operation. Further the MAC performs current scaling using switches and current division where the current switches occupy minimum size transistors requiring a small area to implement that renders it compatible with MRAM such as a magnetic tunnel junction device. The MAC is hierarchically extended for increased number of bits to provide a delay implementation using orthogonal vector and current addition.
Public/Granted literature
- US20210342121A1 LOW AREA MULTIPLY AND ACCUMULATE UNIT Public/Granted day:2021-11-04
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