Invention Grant
- Patent Title: Memory repair using optimized redundancy utilization
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Application No.: US17356647Application Date: 2021-06-24
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Publication No.: US11495314B2Publication Date: 2022-11-08
- Inventor: Chien-Hao Huang , Cheng-Yi Wu , Katherine H. Chiang , Chung-Te Lin
- Applicant: Taiwan Semiconductor Manufacturing Company Limited
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company Limited
- Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
- Current Assignee Address: TW Hsinchu
- Agency: The Marbury Law Group, PLLC
- Main IPC: G11C29/10
- IPC: G11C29/10 ; G11C29/44 ; G11C29/18 ; G11C29/00 ; G11C29/36 ; G11C29/12

Abstract:
A semiconductor device is provided, which contains a memory bank including M primary word lines and R replacement word lines, a row/column decoder, and an array of redundancy fuse elements. A sorted primary failed bit count list is generated in a descending order for the bit fail counts per word line. A sorted replacement failed bit count list is generated in an ascending order of the M primary word lines in an ascending order. The primary word lines are replaced with the replacement word lines from top to bottom on the lists until a primary failed bit count equals a replacement failed bit count or until all of the replacement word lines are used up. Optionally, the sorted primary failed bit count list may be re-sorted in an ascending or descending order of the word line address prior to the replacement process.
Public/Granted literature
- US20220223218A1 MEMORY REPAIR USING OPTIMIZED REDUNDANCY UTILIZATION Public/Granted day:2022-07-14
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