Invention Grant
- Patent Title: Gate driver on array circuit layout
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Application No.: US16627785Application Date: 2019-10-30
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Publication No.: US11488557B2Publication Date: 2022-11-01
- Inventor: Liuqi Zhang , Baixiang Han
- Applicant: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
- Applicant Address: CN Shenzhen
- Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
- Current Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
- Current Assignee Address: CN Shenzhen
- Priority: CN201910862779.0 20190912
- International Application: PCT/CN2019/114173 WO 20191030
- International Announcement: WO2021/046987 WO 20210318
- Main IPC: G09G3/20
- IPC: G09G3/20 ; G09G3/36

Abstract:
A gate driver on array (GOA) circuit layout is provided, including a plurality of driving thin-film transistor units, wherein each of the driving thin-film transistor units includes a wiring side and a capacitor side, and any two adjacent driving thin-film transistor units are spaced apart and connected in series with each other; and a plurality of first capacitor areas, wherein each of the first capacitor areas is disposed between two adjacent capacitor sides of the driving thin-film transistor units. The GOA circuit layout according to the present invention increases heat dissipation area for the driving thin-film transistors, which is more advantageous for heat dissipation. On the other hand, because of sufficient use of the first capacitor areas, a size of layout is basically not increased.
Public/Granted literature
- US20210358441A1 GATE DRIVER ON ARRAY CIRCUIT LAYOUT Public/Granted day:2021-11-18
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