A level shifter includes: a first inverter configured to receive an input signal in a low voltage domain and shift the input signal from the low voltage domain to a first output signal at a first output terminal in a high voltage domain higher than the low voltage domain in response to a logical high state of a first clock signal in the low voltage domain; a second inverter configured to receive a complement of the input signal and shift the complement of the input signal from the low voltage domain to a second output signal at a second output terminal in the high voltage domain in response to the logical high state; a first NMOS sensing transistor and a second NMOS sensing transistor; a PMOS transistor configured to equalize the first output signal and the second output signal in response to a logical low state of the first clock signal.