Invention Grant
- Patent Title: Non-volatile memory device having low-k dielectric layer on sidewall of control gate electrode
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Application No.: US16794715Application Date: 2020-02-19
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Publication No.: US11444208B2Publication Date: 2022-09-13
- Inventor: Tae Whan Kim , Jun Gyu Lee , Hyun Soo Jung
- Applicant: INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY
- Applicant Address: KR Seoul
- Assignee: INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY
- Current Assignee: INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY
- Current Assignee Address: KR Seoul
- Agency: Sughrue Mion, PLLC
- Priority: KR10-2019-0020431 20190221
- Main IPC: H01L21/66
- IPC: H01L21/66 ; H01L29/792 ; G11C16/14 ; H01L29/423 ; H01L27/11565

Abstract:
A non-volatile memory device is provided. The non-volatile memory device comprises a semiconductor channel layer, a tunneling layer, a charge trap layer, and a blocking insulating layer arranged in sequence. A plurality of control gate electrodes are disposed on the blocking insulating layer. An inter-cell insulating layer is disposed between the control gate electrodes. A spacer insulating film is disposed between the control gate electrode and the inter-cell insulating layer, and the spacer insulating film has a lower dielectric constant than the inter-cell insulating layer. The charge trap layer extends under the plurality of control gate electrodes and is disposed under the inter-cell insulating layer and the spacer insulating film.
Public/Granted literature
- US20200274001A1 NON-VOLATILE MEMORY DEVICE HAVING LOW-K DIELECTRIC LAYER ON SIDEWALL OF CONTROL GATE ELECTRODE Public/Granted day:2020-08-27
Information query
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